1. Technical Field
The present disclosure relates to the manufacture of integrated circuits and more particularly to the manufacture of a stack of integrated circuit chips.
2. Description of the Related Art
The interconnection of integrated circuits has become more and more complex with the increasing complexity of the integrated circuits. In order to minimize as much as possible the area necessary to interconnect integrated circuits, it is generally necessary to provide interconnection means such as chip carriers or high-density integrated circuit cards.
For years, the realization techniques of three-dimensional integrated circuits have been seen as the ideal solution to reduce the surface occupied by an ensemble of interconnected integrated circuits. However, various technological constraints prevented the rapid implementation of such a solution.
Conventionally, a three-dimensional integrated circuit is a stack of two or more semiconductor chips in which integrated circuits are embedded. Identical or heterogeneous integrated circuits can be stacked to obtain a high-density 3D circuitry, for example a stack of N memory chips allowing an extended memory array to be realized within a reduced volume.
Stacked integrated circuits are often realized at wafer level, that is to say when the chips—also called dies—have not yet been separated from the wafer within which they were manufactured. The wafer-on-wafer stacking methods comprise stacking two or more wafers that are aligned, interconnected and bonded, and then cut to obtain discrete stacked integrated circuits.
To that end, through-wafer vias are conventionally created before the different wafers are bonded. The wafers can be bonded either before or after a thinning step and can be bonded either front face-to-front face or front face-to-back face. The conventional wafer bonding methods thus include the simultaneous (i.e., at the time of bonding) electrical interconnection of contact pads realized either on a front face or on a back face of the wafers, or both faces. These methods are not very practical to implement when several wafers are stacked. After a step of alignment of the different wafers, the bonding and interconnection of the wafers is a delicate operation due to their large sizes. In addition, the interconnect material, for example a solder, does not offer the flexibility and ductility that may be desired for assembling large wafers. Finally, the fabrication of through vias in each wafer requires various steps and is often complex and costly to implement. Thus, it is expected that the control of three-dimensional interconnect and alignment techniques will be a major challenge in the near future.
Various different methods have been proposed in order to manufacture through vias, such as the method proposed in U.S. Patent Application No. 2005/0101054. This method comprises forming a trench on the top of a semiconductor wafer. The trench is then filled with a dielectric material. The wafer is then thinned until the bottom of the trench is reached, thereby forming a region that is electrically insulated from the rest of the wafer, delineated by the insulating trench. The material within the electrically insulated region is then removed and the insulated region is filled with an electrically conductive material, which allows the interconnection of contacts on the front and back faces of the wafer.
Another method, disclosed in U.S. Patent Application No. 2008/0203556 proposes an opposite approach. A wafer of a conductive material is used here. Patterned trenches are, as previously, formed and then filled with a dielectric material. The trenches thereby insulate the conductive material that they surround from the rest of the conductive wafer, this material thus forming an interconnection between contacts on the front and back faces.
In U.S. Pat. No. 6,642,081, a stacked integrated circuit is obtained by bonding the front face of a first wafer to a face of a second wafer and then thinning the back face of the first wafer until a thickness is obtained that is such that portions of conductive plugs go past the back face of the thinned wafer. The extremities of these plugs are then bonded to contact pads situated upon a front face of a third wafer.
The document JP 2002 050 736 A discloses, in relation with its FIGS. 4A to 4D, a method for stacking at least two wafers wherein a hole is made that penetrates into the two wafers and into electrodes of each substrate. The hole is electrically insulated by means of a selective oxide film that does not deposit upon the electrode materials. A conductive material, such as solder, is then injected in the hole to form a link electrode that is in lateral contact with the electrodes of each wafer.
It may be desired to provide an alternative method to that of document JP 2002 050 736 for stacking and interconnecting integrated circuits in a straightforward and reliable manner that does not require a selective oxide.
The document US 2005/0101054 discloses a method of forming a via comprising steps of forming a trench in a wafer, filling the trench with a dielectric material, forming a contact pad (8, 12) above the trench, thinning the wafer from its rear face until the bottom of the trench is reached, removing the semiconductor material inside of the trench so as to create a cavity, then growing metal in the cavity so as to obtain a conductive via that is in head-on electrical contact with the bottom side of the contact pad.